OMNITEL, INC.
486-25
Processor |
80486DX |
Processor Speed |
25MHz |
Chip Set |
OPTI |
Max. Onboard DRAM |
16MB |
Cache |
64/128KB |
BIOS |
Omnitel |
Dimensions |
355mm x 304mm |
I/O Options |
None |
NPU Options |
4167 |
CONNECTIONS |
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Purpose |
Location |
Purpose |
Location |
External battery |
J1 |
Power LED & keylock |
J26 |
Turbo LED |
J11/pins 1 & 2 |
Reset switch |
J31 |
Speaker |
J25 |
|
|
USER CONFIGURABLE SETTINGS |
|||
Function |
Jumper |
Position |
|
» |
Password enabled |
J43 |
Closed |
|
Password disabled |
J43 |
Open |
» |
External cache enabled |
J50 |
Open |
|
External cache disabled |
J50 |
Closed |
» |
POST enabled |
J51 |
Closed |
|
POST disabled |
J51 |
Open |
» |
Battery select internal |
J52 |
pins 1 & 2 closed |
|
Battery select external |
J52 |
pins 2 & 3 closed |
» |
BIOS type select 27256 |
J60 |
pins 2 & 3 closed |
|
BIOS type select 27512 |
J60 |
pins 1 & 2 closed |
Note:The location of jumpers J50 & J51 are unidentified. |
DRAM CONFIGURATION |
||||
Size |
Bank 0 |
Bank 1 |
Bank 2 |
Bank 3 |
1MB |
(4) 256K x 9 |
NONE |
NONE |
NONE |
2MB |
(4) 256K x 9 |
(4) 256K x 9 |
NONE |
NONE |
3MB |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 256K x 9 |
NONE |
4MB |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 256K x 9 |
4MB |
(4) 1M x 9 |
NONE |
NONE |
NONE |
5MB |
(4) 256K x 9 |
(4) 1 M x 9 |
NONE |
NONE |
6MB |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 1M x 9 |
NONE |
7MB |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 1M x 9 |
8MB |
(4) 1M x 9 |
(4) 1M x 9 |
NONE |
NONE |
9MB |
(4) 256K x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
NONE |
10MB |
(4) 256K x 9 |
(4) 256K x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
12MB |
(4) 1M x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
NONE |
13MB |
(4) 256K x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
16MB |
(4) 1M x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
(4) 1M x 9 |
CACHE CONFIGURATION |
||
Size |
Bank 0 |
Bank 1 |
64KB |
(8) 8K x 8 |
NONE |
128KB |
(8) 8K x 8 |
(8) 8K x 8 |
CACHE JUMPER CONFIGURATION |
|||||
Size |
J44 |
J45 |
J46 |
J47 |
J48 |
64KB |
Open |
Open |
1 & 2 |
1 & 2 |
1 & 2 |
128KB |
Closed |
Closed |
2 & 3 |
2 & 3 |
2 & 3 |
Note: Pins designated should be in the closed position. |